In the process manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called "metalization", and is performed using a number of different photolithographic and deposition techniques.
One metalization process, which is called the "damascene" technique starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the dielectric layer and is photolithographically processed to form the pattern of the first channels. An anisotropic dielectric etch is then used to etch out the channel dielectric layer to form the first channel openings. The damascene step photoresist is stripped and a barrier layer is deposited to coat the walls of the first channel opening to ensure good adhesion and to act as a barrier material to prevent diffusion of such conductive material into the dielectric layer and the semiconductor devices (the combination of the adhesion and barrier material is collectively referred to as "barrier layer" herein). A seed layer is then deposited on the barrier layer to coat the barrier layer and form a conductive material base, or "seed", for subsequent deposition of conductive material. A conductive material is deposited in the first channel openings to fill the opening and then is subjected to a chemical-mechanical polishing process which removes the material above the first channel dielectric layer and damascenes the conductive material in the first channel openings to form the first channels.
For multiple layers of channels, another metalization process, which is called the "dual damascene" technique, is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene technique starts with the deposition of a thin stop nitride over the first channels and the first channel dielectric layer. Subsequently, a separating dielectric layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed dielectric in the via area of the via nitride. A second damascene step photoresist is placed over the second channel dielectric layer and is photolithographically processed to form the pattern of the second channels. An anisotropic dielectric etch is then used to etch the second channel dielectric layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. A barrier layer is then deposited to coat the via openings and the second channel openings. Next, a seed layer is deposited on the barrier layer. This is followed by a deposition of the conductive material in the second channel openings and the via openings to form the second channel and the via. A second chemical-mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by a cylindrical via.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through dielectrics, such as oxide. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor substrate. To prevent diffusion, materials such as tantalum nitride (TaN), or titanium nitride (TiN) are used as barrier materials for copper.
Thus, a thin adhesion layer formed of an adhesion material, such as titanium, is first deposited on the dielectrics or vias to ensure good adhesion and good electrical contact of the subsequently deposited barrier layers to underlying doped regions and/or conductive channels. Barrier layer stacks formed of barrier materials such as tantalum/tantalum nitride (Ta/TaN) and titanium/titanium nitride (Ti/TiN) have been found to be useful as barrier material combination for copper interconnects.
The barrier and seed layers for copper interconnect in a damascene process are typically deposited by physical vapor deposition (PVD) or derivatives of PVD techniques. A popular method is ionized metal deposition which is performed at a low pressure, 20 millitorr (mT) to 100 mT, to maintain high ionization efficiency.
A common problem associated with most of these deposition techniques is poor sidewall step coverage. In effect, the layer thickness is much higher in wide-open areas, such as on top of the channel dielectric layer and in the upper portion of the sidewalls of the channels and vias than in the lower portion of the sidewalls of the channels and vias. To guarantee a required minimum layer thickness anywhere in the channel or vias, including at the lower portion of the sidewalls, the layer thickness in wide-open areas must be much higher. As the width of the channels and vias have decreased in size due to the size reduction in the semiconductor devices, an excessively thick layer in the wide-open areas interferes with the subsequent filling of the channel and vias with conductive materials.
A solution, which would provide better step coverage for layers in channel or vias and improve the subsequent filling of the channel or vias by conductive materials, has long been sought, but has eluded those skilled in the art. As the semiconductor industry is moving from aluminum to copper and other type of materials with greater electrical conductivity and thinner channels and vias, it is becoming more pressing that a solution be found.